With the rapid development of semiconductor manufacturing technology, the technical node of the conventional integrated circuits (ICs) has been continuously shrunk. The critical dimension (CD) of the IC devices has become smaller and smaller. Correspondingly, the fabrication technique of the IC devices has been continuously improved so as to enhance the performances of the IC devices.
For example, in an MOS transistor, a metal layer is usually formed between a high-dielectric constant (high-K) dielectric layer and a metal gate to obtain a desired threshold voltage to improve the device performance. However, with the continuous shrinking of the CD, the conventional planar MOS transistors are unable to match the performance requirements of IC devices. For example, the control ability of the planar CMOS transistors to their channel regions has become relatively weak; and a severe leakage current issue may occur. Thus, replacing the conventional CMOS transistors with multi-gate devices has attracted more and more attentions.
Fin field-effect transistors (FinFETs) are a typical type of multi-gate devices. FIG. 1 illustrates an existing FinFET. As shown in FIG. 1, the FinFET includes a semiconductor substrate 1; a fin 3 on the semiconductor substrate 1; a silicon oxide layer 2 on the semiconductor substrate 1; a gate dielectric layer (not shown) crossing over the fin 3 and a gate 4 on the silicon oxide layer 2; inter-fin sidewall spacers 6 at both sides of the fin 3 and gate sidewall spacers 5 on both sides of the gate 4; and source/drain 31 in the fin 3 at two sides of the gate 4 and the gate-sidewall spacer 5, respectively.
Portions of the top and two side surfaces of the fin 3 that are in contact with the gate 4 form a channel region of the FinFET. That is, such a device structure enables the FinFET to have the functions of multi-gates simultaneously. Thus, the drive current of the FinFET is increased; and the performance of the FinFET is enhanced.
However, with the continuous development of the IC technology, the CD of the devices is continuously reduced; and the device density is continuously increased. Thus, higher requirements of ICs have been brought out. Therefore, the existing FinFETs may be unable to match the development of the ICs. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems in the art.